Hardware-Accelerated Biomedical Signal Processor
Designed and optimised an adaptive LMS FIR filter to eliminate 60Hz powerline interference from clinical ECG signals, then compiled the solution to synthesisable VHDL and verified it on an Intel DE10-Lite FPGA using a custom 32-bit fixed-point architecture.
Adaptive LMS FIR Filter for Clinical ECG Denoising
Module: EIE 527 — Digital Signal Processing | Research & FPGA Prototyping
A complete end-to-end hardware signal processing pipeline — from mathematical filter theory to a synthesised, verified VHDL core running on a physical FPGA. The goal: eliminate 60Hz powerline interference (a persistent noise source in clinical environments) from real Electrocardiogram (ECG) signals without distorting the heartbeat's diagnostic morphology.
Why Adaptive? Why FIR?
Static notch filters fail under real-world conditions — slight frequency drift and patient impedance variation shift the interference out of a fixed filter's rejection band. This project uses an LMS (Least Mean Squares) adaptive FIR filter that continuously learns the noise signature and cancels it in real time using stochastic gradient descent on the Mean Square Error.
A Finite Impulse Response (FIR) architecture was deliberately chosen over IIR to guarantee strictly linear phase — every ECG component (P-wave, QRS complex, T-wave) experiences the same time delay, preserving clinical timing accuracy essential for diagnosis.
Multi-Objective Optimisation
Two parameters govern the filter's performance. A systematic design-space exploration determined the optimal combination:
| Parameter | Value | Rationale |
|---|---|---|
| Step-size μ | 0.01 | Convergence < 500ms; stable artefact-free steady state |
| Filter order N | 32 | Full 60Hz cancellation within Intel DE10-Lite resource budget |
- μ = 0.0001 → too slow; ECG distorted for several seconds.
- μ = 0.1 → near-instant but introduces high-frequency oscillations.
- μ = 0.01 → the "Goldilocks" zone: sub-500ms convergence, clean output.
FPGA Hardware Implementation
Deploying the floating-point MATLAB model to an Intel DE10-Lite FPGA required a complete arithmetic overhaul. Standard 16-bit fixed-point caused severe overflow — insufficient precision to represent the step-size update μ = 0.01. A custom 32-bit fixed-point format fixdt(1, 32, 30) was designed across all accumulators, products, and tap weights, resolving all quantisation crashes.
The optimised Simulink model was then compiled to synthesisable VHDL via MATLAB's HDL Coder toolbox:
| Resource | Count |
|---|---|
| Multipliers | 129 |
| Adders / Subtractors | 131 |
| Main Registers | 63 |
| Total 1-Bit Registers | 2,016 |
Key Outcomes
- Achieved sub-500ms convergence and complete 60Hz cancellation at steady state.
- Confirmed strict linear phase via frequency-domain analysis — zero morphological distortion to the QRS complex or diagnostic P/T-waves.
- Successfully generated and verified synthesisable VHDL on a physical FPGA, proving that ML-inspired adaptive filters are feasible on resource-constrained embedded medical systems.
Tech Stack: MATLAB, Simulink, HDL Coder, VHDL, Intel DE10-Lite FPGA, Fixed-Point Arithmetic, Digital Signal Processing